Classical continuous-time frequency synthesizers, which can be programmed to two or more frequencies, inherently have noisy, frequency-unstable warm-up times during the reprogramming process. The same is true during initial power-up of the classical continuous-time frequency synthesizer. The warm-up time for a programmable frequency synthesizer is considered the time taken by the frequency synthesizer to switch from one operating frequency to a second operating frequency within a desired frequency lock range (e.g.,.+-.10 Hz from the desired second operating frequency), or the time period needed to achieve a desired power-up frequency within a desired frequency lock range.
One source of the noisy warm-up time can arise from the combination of a pulse-width modulated sink-source-float phase error detector with a continuous-time lead-lag network. Such a combination is inherently noisy. A further disadvantage of using the continuous-time lead-lag network is a requirement for external (non-integratable) components to implement a practicable lead-lag network. Communication systems which utilize a frequency synthesizer of this type are adversely affected by the added cost of the external components, are inefficient in power consumption, thereby reducing battery life, and are further affected by manufacturing variations in the external components.
Thus, what is needed is an apparatus that overcomes the aforementioned problems. Preferably, the apparatus should be low cost, power efficient and substantially less noisy and unstable during the warm-up time.